1. Field of the Invention
The invention relates in general to the fabrication of a static random access memory (SRAM), and more particularly to a method of fabricating dual gate oxide and a buried contact of an SRAM.
2. Description of the Related Art
SRAM is the speediest semiconductor memory so that it is widely applied in, for example, accessing computer data. At present, SRAM is applied in digital equipment such as mini-computers and microprocessor and for storing system information.
The structure of SRAM is basically divined into memory cell region and periphery circuit region. However, the operation voltage of these two regions is different and therefore the thickness of the gate oxide layer in these two regions is not equal. A single memory cell in the memory cell region is as shown in FIG. 1, which is used for storing data. The periphery circuit region includes numbers of address decoders for decoding the address of the memory cell in the memory cell region and some circuit foe memory operation.
For a typical SRAM, the structure of a single memory cell circuit is as shown in FIG. 1.
Referring to FIG. 1, a typically SRAM memory cell includes resistors R.sub.1, R.sub.2, and metal-oxide-semiconductor (MOS) transistors T.sub.1, T.sub.2, T.sub.3, T.sub.4. The resistor R.sub.1 and the transistor T.sub.1 are connected in serial. The drain region of the MOS transistor T.sub.1 is coupled to the voltage source V.sub.DD and the source region is coupled to the grounding wire V.sub.ss. The resistor R.sub.2 and the MOS transistor T.sub.2 are connected in serial. The drain region and the source region of the transistor T.sub.2 are coupled to the voltage source V.sub.DD and the grounding wire V.sub.ss, respectively.
Moreover, in the node A, there are the gate of the MOS transistor T.sub.2 and the drain regions of the MOS transistor T.sub.1 and the MOS transistor T.sub.3 connected. In the node B, there are the gate of the MOS transistor T.sub.1 and the drain regions of the MOS transistor T.sub.2 and the MOS transistor T.sub.4 connected. The gate electrodes of the MOS transistors T.sub.3, T.sub.4 are both couple to the word line WL. The source regions of the MOS transistors T.sub.3, T.sub.4 are coupled to the bit line BL and the complementary bit line BL. The transistor T1 and the transistor T2 are used as drivers and the transistors T3 and the transistor T4 are used as access transistors for SRAM data access. The resistors R1 and R2 are used for loading.
Generally, node A and node B in FIG. 1 are contact window structure. These contact windows are mostly formed above the source/drain regions. For some high integration integrated circuit (IC), this kind of contact window is not satisfied. Therefore, a buried contact for local interconnection is proposed. The buried contact uses less surface area of the wafer. For example, as the buried contact is applied in SRAM, 25% less of surface area is used. Therefore, the buried contact provides high-density devices fairy high efficiency.
FIG. 2A to FIG. 2G illustrates a fabrication method of dual gate oxide and a buried contact of a convention SRAM. The operation voltage of the memory cell region and the periphery circuit region is not equal and therefore the thickness of the gate oxide layer is not the same. The buried contact is connected to a gate electrode of a MOS transistor and drain regions of two MOS transistors.
Referring to FIG. 2A, on a semiconductor substrate 200, a device isolation structure, such as field oxide 204 is formed. The semiconductor substrate 200 includes a memory cell region 201 and a periphery circuit region 202. The memory cell region 201 is for forming SRAM memory cells and the periphery circuit region 202 includes address decoders and circuits related to memory operation. Address decoders are used for decoding the address of the memory cells at the memory cell region 201.
Then, processes for forming gate oxide is performed. The gate oxide layer of the periphery circuit region 202 of SRAM is formed in two stages. First, a gate oxide layer 206 is first formed on the memory cell region 201 at the surface of semiconductor substrate 200. A gate oxide layer 207 is simultaneously formed on the periphery circuit region. The gate oxide layers are formed by thermal oxidation and have a thickness of about 95 .ANG..
Next, referring to FIG. 2B, a photoresist layer 208 is formed to cover the periphery circuit region 202 to cover the gate oxide layer 207 at the periphery circuit region 202.
Next, referring to FIG. 2C, the gate oxide layer 206 is removed from the memory cell region 201. The photoresist layer 208 is then removed so that the gate oxide layer 207 on the periphery circuit region 202 is exposed.
However, using the photoresist layer 208 to cover the gate oxide layer 207 on the periphery circuit region 202 influences the quality of the gate oxide layer 207 and causes the problem of incomplete removing of the photoresist layer 208.
Next, referring to FIG. 2D, a second stage of forming the gate oxide layer is performed. On the memory cell region 201 of the semiconductor substrate 200, a gate oxide layer 209 is formed by thermal oxidation. The gate oxide layer 209 has a thickness of about 65 .ANG.. Simultaneously, the gate oxide layer 207 at the periphery circuit region 202 is continuously oxidized. The gate oxide layer 207 becomes a gate oxide layer 207a, having a thickness of about 120 .ANG.. Consequently, the dual gate oxide layer is formed. The gate oxide layer 209 at the memory cell region 201 has a thickness of about 65 .ANG. and the gate oxide layer 207a at the periphery circuit region 202 has a thickness of about 120 .ANG..
The gate oxide layer 207a at the periphery circuit region 202 is formed in two stages. First, a gate oxide layer 207 having a thickness of 95 .ANG. is formed. Secondly, the gate oxide layer 207 is further oxidized to have a thickness of about 120 .ANG. to become a gate oxide layer 207a. The thickness of the gate oxide layer 207a can not be precisely controlled and the quality is not reliable since the gate oxide layer 207a is formed by two stages.
Referring to FIG. 2E, a conductive layer 210 is formed over the whole semiconductor substrate 200. The material of the conductive layer 210 can be, for example, doped polysilicon. On the conductive layer 210, a photoresist layer 212 with a pattern of buried contact region 214 is formed. The buried contact window region 214 is located at the memory cell region 214 and connects the gate of one MOS transistor and the drain regions of two MOS transistors.
Next, referring to FIG. 2F, using the photoresist layer 212 as an etching mask, the conductive layer 210 is etched to form a conductive layer 210a so that the gate oxide layer 209 at the contact window region 214 is exposed. The photoresist layer 212 is then stripped.
Next, referring to FIG. 2G, using the conductive layer 210a as a mask, a portion of the gate oxide layer 209 is stripped so that the surface of the semiconductor substrate 200 is exposed. The remained gate oxide layer at the memory cell region 201 is resented as a gate oxide layer 209a.
The sequential processes are then continued to complete the SRAM.